发明名称 Low complexity implementation of a Viterbi decoder with near optimal performance
摘要 A method and system for low-complexity implementation of a Viterbi Decoder with near optimal performance has been disclosed. The Viterbi decoding technique is diagrammatically represented as a trellis. The trellis includes various states at different time instants, and branches connecting these states. Each state has an associated state metric and a survivor path sequence, whereas each branch has a branch metric. The state metric for each current state is checked for crossing a predefined limit. If it crosses the predefined limit, the state metric is updated with a new metric that is obtained by subtracting a constant value from the state metric. Thereafter, the method finds a common path in the trellis at each state and updates the survivor path sequence of each state. The Most Significant Bits (MSBs) of the survivor path sequences of the states at a particular time instant are computed and the original data is decoded, based on the count of ‘0s’ and ‘1s’ in the MSBs.
申请公布号 US8009773(B1) 申请公布日期 2011.08.30
申请号 US20080080597 申请日期 2008.04.04
申请人 HELLOSOFT INDIA PVT. LTD. 发明人 KANKIPATI SRIRAM;BARMAN KAUSHIK;OJHA KRUSHNA PRASAD
分类号 H04L27/06 主分类号 H04L27/06
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