发明名称 SEMICONDUCTOR PACKAGE
摘要 Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.
申请公布号 US2011193215(A1) 申请公布日期 2011.08.11
申请号 US201113023565 申请日期 2011.02.09
申请人 RENESAS ELECTRONICS CORPORATION 发明人 TOYAMA MASAHIRO;UEMATSU YUTAKA;OSAKA HIDEKI
分类号 H01L23/50 主分类号 H01L23/50
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