发明名称 3D VERTICAL TYPE MEMORY CELL STRING WITH SHIELD ELECTRODE ENCOMPASSED BY ISOLATING DIELECTRIC STACKS, MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF
摘要 PURPOSE: A 3D vertical type memory cell string with shield electrode surrounded by a isolation insulating layer stack, a memory array using the same and a manufacturing method thereof are provided to solve the threshold voltage dissemination problem of stacks by injecting charges into the charge storage node in the isolation insulating layer stack as well as completely eliminate electrical interference which occurs in semiconductor bodies in both sides of each trench. CONSTITUTION: Two or more electrode stacks are separated by one or more trenches at a certain distance on a semiconductor substrate(1) and are formed by repeatedly laminating an insulating layer and a conductive material layer(10) to the vertical direction by turns. A gate insulating layer stack includes a charge storage layer which is formed on the top and the side of each electrode stack and the separated space of the substrate. A semiconductor body(5) is formed on the gate insulating layer stack. A shield electrode(27) is formed by placing the isolation insulating layer for each trench on the semiconductor body. The isolation insulating layer includes the charge storage node.
申请公布号 KR101056113(B1) 申请公布日期 2011.08.10
申请号 KR20100063958 申请日期 2010.07.02
申请人 SNU R&DB FOUNDATION 发明人 LEE, JONG HO;SHIN, HYUNG CHEOL
分类号 H01L27/115;H01L21/8247;H01L27/10 主分类号 H01L27/115
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