| 摘要 |
A value held in storage elements coupled to a clock buffer and variably set with a threshold voltage is read out in a state where an analyzing target circuit within an IC operates. An analyzing process specifies an impact of noise in a power supply or ground voltage of the clock buffer and a location where the impact is large, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set logic value and each storage element that is a read target. A constraint condition for placement of constituent elements of the IC and routing therein is created from results of the analyzing process, and a re-placement or re-routing process re-places or re-routes the constraint condition to reduce the noise.
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