| 摘要 |
PROBLEM TO BE SOLVED: To provide an arithmetic processor including an ALU (arithmetic logic unit) having a plurality of arithmetic circuits each for performing a group of associated arithmetic operations such as finite field operations or modular integer operations. SOLUTION: The ALU has an operand input data bus for receiving operand data thereon and a result data output bus for returning the results of the arithmetic operations thereon. A register file is coupled to the operand data bus and the result data bus. The register file is shared by the plurality of arithmetic circuits. Further a controller is coupled to the ALU and the register file, the controller selecting one of the plurality of arithmetic circuits in response to a mode control signal requesting an arithmetic operation and for controlling data access between the register file and the ALU and whereby the register file is shared by the arithmetic circuits. COPYRIGHT: (C)2011,JPO&INPIT
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