| 摘要 |
A circuit for performing a discrete cosine transformation (DCT) of input signals (416) includes a forward adder-tree module (402), a first set of multiplexers (404), a shared flow-graph module (406), an inverse adder-tree module (408), and a second set of multiplexers (410) coupled in series. In operation, the multiplexers (404) are configured to process input signals via the forward adder-tree module (402) and the shared flow-graph module (406) to perform a forward DCT of the input signals (416) or via the shared flow-graph module (406) and the inverse adder-tree module (408) to perform an inverse DCT of the input signals (416). |
