发明名称 |
Method of manufacturing stacked wafer level package |
摘要 |
A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.
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申请公布号 |
US2011129960(A1) |
申请公布日期 |
2011.06.02 |
申请号 |
US20110929703 |
申请日期 |
2011.02.09 |
申请人 |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
发明人 |
PARK SEUNG WOOK;KWEON YOUNG DO;KIM JIN GU;HONG JU PYO;LEE HEE KON;JEON HYUNG JIN;LI YUAN JING;LEE JONG YUN |
分类号 |
H01L21/50 |
主分类号 |
H01L21/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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