发明名称 CIRCUIT TO GUARANTEE OPERATING PLL OF CENTRAL PROCESSING UNIT
摘要 PURPOSE: A circuit for compensating the PLL operation of a CPU is provided to stably control the operation of a system and to prevent the interruption of a CPU by normally completing the PLL operation. CONSTITUTION: A reset signal generator(200) generates a reset signal. A CPU(210) embeds a PLL(Phase Lock Loop)(212) and is operated according to a clock signal. If there is the reset signal, the CPU stops the operation of PLL and generates the system reset signal. If the reset signal is released, the CPU operates the PLL and generates a reset interrupt signal.
申请公布号 KR20110058235(A) 申请公布日期 2011.06.01
申请号 KR20090114948 申请日期 2009.11.26
申请人 KEFICO CORPORATION 发明人 KO, HYUN;RYU, TAE GYU
分类号 G06F1/24;H03L7/08 主分类号 G06F1/24
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