发明名称 |
Bias circuit for common-mode and semiconductor process voltage and temperature optimization for a receiver assembly |
摘要 |
A receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.
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申请公布号 |
US7952398(B2) |
申请公布日期 |
2011.05.31 |
申请号 |
US20070741115 |
申请日期 |
2007.04.27 |
申请人 |
AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE.LTD. |
发明人 |
SALCIDO MANUEL;PATTERSON J. KEN;CYNKAR THOMAS EDWARD |
分类号 |
H03B1/00 |
主分类号 |
H03B1/00 |
代理机构 |
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代理人 |
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地址 |
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