| 发明名称 |
WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE |
| 摘要 |
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
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| 申请公布号 |
US2011108896(A1) |
申请公布日期 |
2011.05.12 |
| 申请号 |
US201113007356 |
申请日期 |
2011.01.14 |
| 申请人 |
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED |
发明人 |
FENG TAO;HEBERT FRANCOIS;SUN MING;HO YUEH-SE |
| 分类号 |
H01L29/78;H01L21/78 |
主分类号 |
H01L29/78 |
| 代理机构 |
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代理人 |
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| 主权项 |
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