CAPACITIVE VOLTAGE DIVIDER

摘要

A capacitive voltage divider arrangement (100) comprising a first voltage divider (101) and a second voltage divider (102), a first parasitic capacitance (Cp1) and a second parasitic capacitance (Cp2) being formed between the first capacitive voltage divider (101) and the second capacitive voltage divider (102). The first capacitive voltage divider (101) comprises a terminal (110) for a signal; a first capacitance (C1), via which the terminal (110) may be coupled to a reference potential (U0); a second capacitance (C2); a third capacitance (C3) that may be coupled to the reference potential (U0); the second capacitance (C2) being coupled in between the terminal (110) and the third capacitance (C3). The second capacitive voltage divider (102) comprises a first compensation capacitance (C1), via which the terminal (110) may be coupled to the reference potential (Uo), the first compensation capacitance (C1) further being coupled to the terminal (110) via the first parasitic capacitance (Cp1); a second compensation capacitance (C2); a third compensation capacitance (C3) that may be coupled to the reference potential (Uo), the second compensation capacitance (C2) being coupled in between the terminal (110) and the third compensation capacitance (C3), and the second parasitic capacitance (Cp2) coupling the third capacitance (C3), at a terminal coupled to the second capacitance (C2), to the third compensation capacitance (C3), at a terminal coupled to the second compensation capacitance (C2).