发明名称 |
Method and system of cycle slip framing in a deserializer |
摘要 |
A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.
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申请公布号 |
US7936854(B2) |
申请公布日期 |
2011.05.03 |
申请号 |
US20080103622 |
申请日期 |
2008.04.15 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
FOLEY SEAN;LOMBAARD CAZEL;BLAKE TONY;SCOTT PAUL;SARDI MOHAMED |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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