BANK STRUCTURE OF FPGA BOARD FOR SEMICONDUCTOR VERIFICATION

摘要

The present invention relates to a bank structure of an FPGA board for semiconductor verification. A programmable logic device (PLD) board for semiconductor design verification comprises: at least one FPGA board provided with an FPGA device having a logic circuit for semiconductor verification, and with a plurality of connectors for inputting/outputting signals to/from the FPGA device. A plurality of input/output pins of the FPGA device are divided into an arbitrary number of groups, each group being allocated to each of a plurality of locations. The connectors on the FPGA board are also allocated to a plurality of locations, corresponding to the respective locations where the input/output pins are allocated. The locations where the input/output pins of the FPGA device are allocated are correspondingly integrated with the locations where the connectors are allocated. The FPGA board configured as above optimizes connectivity between the FPGA device and the connectors.