发明名称 |
Interconnect structure of semiconductor integrated circuit, and design method and device therefor |
摘要 |
A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
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申请公布号 |
US7913221(B2) |
申请公布日期 |
2011.03.22 |
申请号 |
US20070907999 |
申请日期 |
2007.10.19 |
申请人 |
PANASONIC CORPORATION |
发明人 |
MIYASHITA HIROFUMI;KABUO CHIE;IWAUCHI NOBUYUKI;MATSUMURA YOICHI;KIMURA FUMIHIRO;GOU TATSUO;HASHIMOTO YUKIJI |
分类号 |
G06F17/50;H01L21/3205;H01L21/768;H01L21/82;H01L21/822;H01L23/522;H01L23/532;H01L27/04 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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