| 摘要 |
PURPOSE: A method for manufacturing an analysis sample for detecting a metal wiring defect of a semiconductor device is provided to easily detect the cause of a defect by maximally preventing the damage to a sample for analyzing the defect of the device. CONSTITUTION: A lower metal wiring line is formed on a silicon substrate. An insulation layer is formed on the front side including a lower metal wiring line. An upper metal wiring line is formed on the insulation layer in a vertical direction to the lower metal wiring line. The insulation layer is exposed by etching the upper metal wiring line. The insulation layer is selectively etched to have a preset thickness.
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