发明名称 |
Opportunistic Timing Control in Mixed-Signal System-On-Chip Designs |
摘要 |
An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
|
申请公布号 |
US2011043251(A1) |
申请公布日期 |
2011.02.24 |
申请号 |
US20090630999 |
申请日期 |
2009.12.04 |
申请人 |
KUSUDA YOSHINORI;COLN MICHAEL;CARREAU GARY |
发明人 |
KUSUDA YOSHINORI;COLN MICHAEL;CARREAU GARY |
分类号 |
H03K19/00 |
主分类号 |
H03K19/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|