| 摘要 |
PURPOSE:To enable to check failure of storage operation of the output memory device, by comparing the parity signal added to the input data with the parity signal added to the memory output data. CONSTITUTION:The parity signal F with the input data A is given to the parity coincidence detection circuit 21. After that, the memory 11 reads in the data A with the normal confirmation output H of the read-in control signal circuit 13 and the parity signal K is delivered from the parity addition circuit 16, then the signal K is given to the circuit 21. The circuit 21 returns the parity check read-in end signal L to the control section 1 when the signals F and K are in agreement and the read-in end signal J is obtained at the time delay circuit 15. The control section 1 can judge the correct transfer of the data A to each memory device and the stored data A in this memory 11 correctly, through the return of the signal L. |
