| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To attain lower noise, suppression of temperature rise and power saving in power-on of an ASIC using a clock gating-synchronous reset type synchronous FF or in standby of the ASIC using a reset terminal. <P>SOLUTION: The ASIC including a synchronous reset FF circuit or a circuit including a synchronous reset FF circuit controlled by a clocked gate includes a reset terminal to which an external reset signal can be input from the outside of the ASIC; and a reset control circuit for inputting, upon power-on, a power-on reset signal by a reset IC to at least the reset terminal, and generating a reset signal for initializing circuits (except the reset control circuit) within the ASIC on the basis of the time when the external reset signal shifts from an active state to an inactive state. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
