SEMICONDUCTOR MEMORY DEVICE

摘要

In order to secure resistance to breakdown of the gates of transistors while holding the internal data of a memory cell without hindering the regularity of layout, in two inverters (401, 402) of a latch of the memory cell (100), the source or drain of a PMOS load transistor (PL1) connected to one memory node (104) is disconnected and the source or drain of an NMOS drive transistor (ND0) connected to another memory node (103) is disconnected.