| 摘要 |
PROBLEM TO BE SOLVED: To reduce manufacturing costs by correcting jitter of a digital signal using a clock signal. SOLUTION: In a decoder 10, a sampling frequency of an ADC 11 is a fixed one and an A-D converted digital signal output by the ADC 11 is subjected to linear interpolation (bilinear interpolation) or bicubic interpolation, so as to make correction such that a digital value in which a sampling point has been shifted caused by horizontal jitter from an original sample point resulting from sampling in synchronization with a video signal, is caused to approach a digital value at the original sampling point. COPYRIGHT: (C)2011,JPO&INPIT
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