发明名称 Memory interface circuit
摘要 An interface circuit comprising: a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit; a second output circuit configured to output the access signal outputted from the first output circuit; and a comparison circuit configured to compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and output a comparison signal indicating whether predetermined access has been performed based on the access signal inputted to the first output circuit, after at least a part of the access signal is inputted to the first output circuit.
申请公布号 EP2237160(A2) 申请公布日期 2010.10.06
申请号 EP20100158321 申请日期 2010.03.30
申请人 SANYO ELECTRIC CO., LTD.;SANYO SEMICONDUCTOR CO., LTD. 发明人 NAGAE, YOSHIHIRO
分类号 G06F13/42 主分类号 G06F13/42
代理机构 代理人
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