发明名称 Semiconductor integrated circuit device and dummy pattern arrangement method
摘要 A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.
申请公布号 US7772070(B2) 申请公布日期 2010.08.10
申请号 US20070711783 申请日期 2007.02.28
申请人 NEC ELECTRONICS CORPORATION 发明人 KITAJIMA HIROYASU;FURUTA HIROSHI;JINBO TOSHIKATSU
分类号 H01L21/8234 主分类号 H01L21/8234
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