| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a cryptographic processing device finding a function given by merging an FL function and an FL<SP>-1</SP>function in a circuit without a feedback loop. <P>SOLUTION: The cryptographic processing device has: a first arithmetic gate that is either an AND gate or an OR gate and is configured to receive a first input bit string and a bit string based on an extended key; a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string; a second arithmetic gate which is a different gate from the first arithmetic gate and is configured to receive an output of the first XOR gate and a bit string based on the extended key; a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string; a third arithmetic gate which is the same type as the first arithmetic gate and is configured to receive an output of the second XOR gate and a bit string based on the extended key; and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
