发明名称 |
SYSTEM AND METHOD FOR ISOLATED NMOS-BASED ESD CLAMP CELL |
摘要 |
The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal. |
申请公布号 |
WO2010074939(A1) |
申请公布日期 |
2010.07.01 |
申请号 |
WO2009US66984 |
申请日期 |
2009.12.07 |
申请人 |
ANALOG DEVICES, INC.;FOLEY, DAVID;ZHU, HAIYANG |
发明人 |
FOLEY, DAVID;ZHU, HAIYANG |
分类号 |
H01L23/62 |
主分类号 |
H01L23/62 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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