| 摘要 |
PURPOSE: A synchronous circuit of a semiconductor memory device is provided to improve operation reliability by generating output data by synchronizing the rising edge of a clock with the center of input data. CONSTITUTION: A rising edge timing control unit(100) receives a clock and generates a control clock. The control clock is transited to a high state in a faster or slower timing than the rising edge. A data clock synchronization unit(10) receives input data in the rising edge of the control clock and outputs the input data. |
