| 摘要 |
<p>A circuit (20) comprises an interface (30) for communicating with another circuit (10). The interface (30) comprises a parallel data bus having a set of data lines (31 ) which are operable in a first data transfer mode in which the set of data lines (31 ) are used to transfer data and in a second data transfer mode in which a sub-set (32) of the data lines are used to transfer data. A mode detection module (50) determines which of the data transfer modes is in use by detecting a state of at least one of the data lines which is only used by the first data transfer mode and detecting a state of at least one line from the sub-set of data lines. The mode detection module (50) can detect logic values received on the data lines at a time when a command having known logic values is expected to be received over the interface and determine the data transfer mode according to which of the data lines the known logic values are detected on.</p> |
