发明名称 |
Structure and method for low resistance interconnections |
摘要 |
A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.
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申请公布号 |
US7737026(B2) |
申请公布日期 |
2010.06.15 |
申请号 |
US20070693153 |
申请日期 |
2007.03.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LI YING;WONG KEITH KWONG-HON |
分类号 |
H01L21/4763 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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