| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the burden on a designer even when assertion descriptions are imperfect. Ž<P>SOLUTION: A logic circuit design verification apparatus includes: an input unit 14 configured to input a circuit description and an assertion description, an extracting unit configured to extract signal names from the circuit description input by the input unit 14, a lack detection unit configured to detect a signal name not included in a postulation and a verification requirement in the assertion description input by the input unit 14 among the signal names extracted by the extracting unit, and an output unit 16 configured to output the signal name detected by the lack detection unit. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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