| 摘要 |
In a preferred embodiment, a CPU extracts a regular structure in a layout of an integrated circuit using layout graphic information, net list information, and constraint information with reference to regularity information of an array-structure, a row-structure, and the like, stored in a magnetic disk storage to evaluate the regular structure, and optimizes the layout of the integrated circuit using the layout graphic information, the net list information, etc., in consideration of the evaluation of the regular structure. Thus, a layout excellent in circuit characteristics and device matching properties, wiring characteristics can be obtained.
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