ADDRESS GENERATION

摘要

Address generation by an integrated circuit (100) is described. An aspect relates generally to an address generator (220) which has first and second processing units (310, 320). The second processing unit (320) is coupled to receive a stage output from the first processing unit (310) and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from -K to -1 for a block size of K, and the second range is from 0 to K- 1.