发明名称 |
METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION |
摘要 |
Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
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申请公布号 |
US2010052730(A1) |
申请公布日期 |
2010.03.04 |
申请号 |
US20090618629 |
申请日期 |
2009.11.13 |
申请人 |
GROCHOWSKI EDWARD;WILKERSON CHRIS;LU SHIH-LIEN L;ANNAVARAM MURALI |
发明人 |
GROCHOWSKI EDWARD;WILKERSON CHRIS;LU SHIH-LIEN L.;ANNAVARAM MURALI |
分类号 |
H03K5/19 |
主分类号 |
H03K5/19 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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