| 摘要 |
There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, Ax, from the first M-bit argument and a first data bit, Bx, from the second M-bit argument, and generates a first conditional carry-out bit, Cx(1), and a second conditional carry-out bit, Cx(0), wherein the Cx(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the Cx(0) bit is calculated assuming the row carry-out bit from the second row is a 0.
|
