发明名称 |
POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM |
摘要 |
A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
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申请公布号 |
US2010005281(A1) |
申请公布日期 |
2010.01.07 |
申请号 |
US20080166139 |
申请日期 |
2008.07.01 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUCHMANN PETER L.;FERRAIOLO FRANK D.;GOWER KEVIN C.;REESE ROBERT J.;RETTER ERIC E.;SCHMATZ MARTIN L.;SPEAR MICHAEL B.;THOMSEN PETER M.;TROMBLEY MICHAEL R. |
分类号 |
G06F9/24 |
主分类号 |
G06F9/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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