发明名称 ENCRYPTION DEVICE USING FPGA WITH MULTIPLE CPU CORES
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an encryption device which can efficiently process transaction accompanied with encryption processing by solving such a problem that is accompanied with insufficient processing capability of CPU cores built in FPGA, which is developed to incorporate a plurality of CPU cores in these days so that these CPU cores work together well while the small number of parts are kept. <P>SOLUTION: The FPGA 100 is provided with a plurality of CPU cores. The CPU core 110 for application processes a plurality of transactions in parallel together with encryption processing that is required by the specified application program. When the encryption processing which needs the execution of processing accompanied with the plurality of transactions to be processed in parallel by the CPU core 110 for application is generated, the CPU 120 for encryption processing executes the generated encryption processing. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2009296195(A) 申请公布日期 2009.12.17
申请号 JP20080146460 申请日期 2008.06.04
申请人 MITSUBISHI ELECTRIC CORP 发明人 SAEKI MINORU
分类号 H04L9/10;G06F9/50;G06F12/14;G06F21/24 主分类号 H04L9/10
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