| 发明名称 |
Device forming a logic gate for detecting a logic error |
| 摘要 |
The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.
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| 申请公布号 |
US2009302883(A1) |
申请公布日期 |
2009.12.10 |
| 申请号 |
US20060921527 |
申请日期 |
2006.06.06 |
| 申请人 |
ETAT FRANCAIS, REPRESENTE' PAR LE SECRETARIAT GENERAL DE LA DEFENSE NATIONALE |
发明人 |
DUFLOT LOIC |
| 分类号 |
H03K19/00;H03K19/003 |
主分类号 |
H03K19/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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