发明名称 Flash memory programming and verification with reduced leakage current
摘要 A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
申请公布号 US7630253(B2) 申请公布日期 2009.12.08
申请号 US20060398415 申请日期 2006.04.05
申请人 SPANSION LLC 发明人 MELIK-MARTIROSIAN ASHOT;RUNNION ED;RANDOLPH MARK;DING MENG
分类号 G11C16/04 主分类号 G11C16/04
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