发明名称 Method of making a transistor with a sloped drain diffusion layer
摘要 Disclosed is that in a method of manufacturing a semiconductor device of the present invention, when first and second P type diffusion layers using as a backgate region, these layers are formed in such a way that their impurity concentration peaks are shifted, respectively. Then, in the backgate region, a concentration profile of a region where an N type diffusion layer is formed is gradually established. After that, impurity ions, which form the N type diffusion layer, are implanted, and thereafter a thermal treatment is performed to diffuse the N type diffusion layer in a y shape at a lower portion of a gate electrode. This manufacturing method makes it possible to implement an electric filed relaxation in a drain region.
申请公布号 US7629214(B2) 申请公布日期 2009.12.08
申请号 US20060392779 申请日期 2006.03.28
申请人 SANYO ELECTRIC CO., LTD. 发明人 OTAKE SEIJI;KIKUCHI SHUICHI
分类号 H01L21/8244 主分类号 H01L21/8244
代理机构 代理人
主权项
地址
您可能感兴趣的专利