CLOCK DELAY CIRCUIT USING CURRENT SOURCE

摘要

PURPOSE: A clock delay circuit using a power source is provided to correct an error in a measurement environment and a manufacture process by controlling a clock signal of a high speed analog to digital converter in the outside. CONSTITUTION: A plurality of current control time delay cell(100) are serially connected and control the delay time of the clock based on an amount of inputted currents. A delay time controller(300) respectively inputs one input bias current quantity corresponding to the delay time of the clock to the current control time delay cell. The delay time controller is comprised of one first n-MOS FET. In the first n-MOS FET, a gate terminal is connected to the current control time delay cell. A drain terminal and the gate terminal are connected to the current source. A source terminal is connected to the ground. The current control time delay cell includes at least one basic CMOS inverter and one transformed inserter into which the n-MOS FET is inserted.