发明名称 Dat processing apparatus and method
摘要 A data processing apparatus is operable to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator and an interleaver memory. The controller is operable, when operating in accordance with an even interleaving process to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out a first set of input data symbols from the interleaver memory on to the sub-carrier signals of an odd OFDM symbol using read addresses determined in accordance with a sequential order of the first set of input data symbols, and to write in a second set of the input data symbols into the interleaver memory at write addresses determined in accordance with the sequential order of the first group of input data symbols. The controller is operable to determine before reading out the first input data symbols from the interleaver memory, whether the read address is valid for a previous OFDM symbol, and to determine before writing the second input data symbols into the interleaver memory, whether the write address is valid for a current OFDM symbol. As such, the interleaver memory size can be minimised to an amount which corresponds to a maximum number of sub-carriers, which are available for an OFDM symbol for any of the operating modes. Application can be found with DVB-T2, which includes a 32K mode.
申请公布号 EP2129066(A2) 申请公布日期 2009.12.02
申请号 EP20090251244 申请日期 2009.05.01
申请人 SONY CORPORATION 发明人 ATUNGSIRI, SAMUEL ASANBENG;TAYLOR, MATTHEW PAUL ATHOL
分类号 H04L27/26;H03M13/27;H04J11/00;H04L1/00;H04N5/44 主分类号 H04L27/26
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