| 摘要 |
A memory device includes a latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal. The memory device further includes a bit cell comprising a storage component, and a write row driver configured to enable write access to the bit cell to store the latched bit value at the storage component for a first phase and a second phase of a cycle of the clock signal, the second phase following the first phase, and a read row driver configured to disable read access to the bit cell for the first phase of the cycle of the clock signal and to enable read access to the bit cell for the second phase of the cycle of the clock signal.
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