发明名称 MULTIPROCESSOR SYSTEM AND MULTIPROCESSOR SYSTEM INTERRUPT CONTROL METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a multiprocessor system that can improve the entire system processing efficiency while assuring an appropriate interrupt response based on an interrupt priority. Ž<P>SOLUTION: The multiprocessor system includes: a plurality of processors each having a register; a plurality of I/O devices; and an interrupt generator. An interrupt control method for the multiprocessor system includes: a setting step in which a corresponding processor sets in a register an interrupt allowance degree that indicates the degree that interrupts are allowed; a report step in which the interrupt generator which has caused a storage unit to store the interrupt priority indicating a priority for an interrupt from each I/O device receives an interrupt request from an I/O device and reports the interrupt request to a plurality of processors together with the interrupt priority of the I/O device; and an interrupt acceptance step in which the interrupt request is accepted by any one of the processors having the register in which a lower interrupt allowance degree is stored as compared to the interrupt priority. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009251802(A) 申请公布日期 2009.10.29
申请号 JP20080097226 申请日期 2008.04.03
申请人 PANASONIC CORP 发明人 OMASA TAKASHI
分类号 G06F13/24 主分类号 G06F13/24
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