Halbleiterbauelement und Versorgungsleitungsanordnungsverfahren

摘要

The semiconductor memory has pad power lines (PVSS1,PVSS1'',PVDD1,PVDD1'') arranged below the lower pads in the pad structures (PVDD,PVSS), in a direction crossing the pad structures to interconnect the pad structures transmitting the same level of electrical power. The sub-pad power lines are arranged in a direction perpendicular to the pad power lines. An independent claim is also included for method of power line arrangement in semiconductor memory.