发明名称 STRUCTURE AND METHOD FOR FORMING A PLANAR SCHOTTKY CONTACT
摘要 A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.
申请公布号 KR20090096459(A) 申请公布日期 2009.09.10
申请号 KR20097012367 申请日期 2007.11.28
申请人 FAIRCHILD SEMICONDUCTOR CORPORATION 发明人 SESSION FRED
分类号 H01L27/095;H01L21/28;H01L21/338;H01L29/872 主分类号 H01L27/095
代理机构 代理人
主权项
地址
您可能感兴趣的专利