| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a design device for a semiconductor integrated circuit that achieves the minimization of a clock skew. <P>SOLUTION: A flip-flop moving means 104 refers to the arrangement result of logic cells and flip-flops and the arrangement/wiring result of a clock distribution circuit, supplying a clock signal to the flip-flops so as to move the flip-flops around a clock drive buffer in the final stage of the clock distribution circuit. A clock distribution circuit rearrangement/wiring means 105 refers to the arrangement result of the logic cells and the flip-flops after moving the flip-flops so as to execute the rearrangement/rewiring of the clock distribution circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
