| 摘要 |
PROBLEM TO BE SOLVED: To guarantee cache coherency and suppress the deterioration of processing efficiency of a system. SOLUTION: Each CPU has a write-back type cache. When receiving a read request to a main memory 86 from the CPU, a read management part 92 permits reading on condition that the data of the requested address is not read by the other CPUs. When the reading of the data is performed by the CPU, a cache line address information maintenance part 94 maintains the address until the data are output to the corresponding CPU. A pending direction part 96 performs pending directions to temporarily stop issuance of requests relevant to reading of the data to the CPUs other than the corresponding CPU, in synchronization with outputting of the data of the address maintained in the cache line address information maintenance part 94 to the corresponding processor. COPYRIGHT: (C)2009,JPO&INPIT
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