| 摘要 |
A reception apparatus (1) in which a multiphase sampling clock signal is generated by a sampling clock signal generation circuit (40) according to the clock signal whose phase is adjusted by a phase adjustment circuit (50). A sampler block circuit (30n) samples data of each bit of a serial data signal at the timing instructed by the sampling clock signal and outputs the sampled data. A phase adjustment amount to the clock signal in the phase adjustment circuit (50) is set so as to cancel the delay time between the generation of the multiphase sampling clock signal in the sampling clock signal generation circuit (40) and the instruction of the sampling timing by the sampling clock signal in the sampler block circuit (30n). ® KIPO & WIPO 2009
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