Fabrication of Compact Semiconductor Packages

摘要

A wafer-level method of fabricating a chip-to-wafer or wafer-to-wafer semiconductor packages includes etching a cavity into a first semiconductor wafer and etching vias in a bottom of the cavity. The cavity and sidewalls of the vias are selectively metallized. The cavity can be used to house either an electrical circuit component or to contain a device die. A second semiconductor wafer is placed over the cavity-side of the first semiconductor and is sealed to the first semiconductor wafer. A backside of the first semiconductor wafer is thinned to expose metallization in the vias and metal is deposited on the backside to form circuit routing paths.