| 摘要 |
PROBLEM TO BE SOLVED: To confirm the validity of timing constraint in the simulation of a logical circuit. SOLUTION: The logical circuit to be simulated includes: a timing network (FF-A, U1) which transmits the logical value change of an input signal in correspondence with an elapse of time or clock number increments; and a specific logical device (FF-B) which receives a timing network output signal TI5 that appears at an exit node of the timing network, and a logical value change or a logical value TI2 after change of the clock. When prescribed constraint information represents a timing constraint that a time period or the demanded number of clock cycles needed for a transition of a signal level change to pass through a signal path in the timing network is equal to or smaller than a prescribed numerical value (or equal to or larger than a prescribed numerical value), it is checked whether or not the signal TI5 input to the specific logical device (FF-B) violates the prescribed constraint information. COPYRIGHT: (C)2009,JPO&INPIT
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