发明名称 METHOD TO CHECK MODEL ACCURACY DURING WAFER PATTERNING SIMULATION
摘要 A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.
申请公布号 US2009182448(A1) 申请公布日期 2009.07.16
申请号 US20080015077 申请日期 2008.01.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 MANSFIELD SCOTT M.;LIEBMANN LARS W.;TALBI MOHAMED
分类号 G06F17/00 主分类号 G06F17/00
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