发明名称 METHOD AND APPARATUS FOR DETECTING STATE OF CIRCUIT UNDER TEST
摘要 PROBLEM TO BE SOLVED: To provide a method and an apparatus for detecting a state of a circuit under test, capable of simply modeling the state of the circuit under test and easily evaluating the state of the circuit under test. SOLUTION: The apparatus comprises: a power supply circuit 3 for supplying a variable voltage VDD(t) which varies temporally, to the circuit under test 2 which has a plurality of CMOS transistors (semiconductor devices); an input signal supplying section 5 for supplying an input voltage Vi(t) which is lower than the variable voltage VDD(t) and varies temporally, to an input terminal T1 of the circuit under test 2 in a period starting before or after supplying the variable voltage VDD(t); and a control section 7 for collecting temporally varying operation states of one or more object transistors among the plurality of transistors, and detecting at least a portion of circuit information including the object transistor from the collected operation states. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009156675(A) 申请公布日期 2009.07.16
申请号 JP20070333981 申请日期 2007.12.26
申请人 TOKYO METROPOLITAN UNIV;TAMA TLO LTD 发明人 MIURA YUKIYA
分类号 G01R31/26 主分类号 G01R31/26
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